("TPL") Motion to Correct its Preliminary Infringement Contentions (reformatted)
I. INTRODUCTION
This provides a consolidated reply to Defendants' oppositions to Plaintiff Technology Properties Limited, Inc.'s ("TPL") Motion to Correct its Preliminary Infringement Contentions ("PICs"). Defendants do not oppose TPL's motion as it relates to conforming the text of the PICs to the claim charts, except that Toshiba (but not NEC or MEI) opposes any correction to the PICs as it relates to the '148 patent because Toshiba believes the claim charts do not show evidentiary support a claim for infringement of the '148 patent. Since the purpose of PICs is to provide
notice of the plaintiff's contentions, rather than evidentiary support, this portion of the motion
should plainly be granted. Defendants NEC and Toshiba also assert that it is per se improper for TPL to provide
claim charts for representative chips of the chip family, rather than claim charts for all members of all accused chip families. MEI, however, acknowledges that this is an appropriate way to proceed and actually cites case authority from the Northern District of California, which explains the perfectly logical and rational reason why this is an appropriate and beneficial way to proceed.
TPL has already provided Defendants with 600 claim charts. If TPL were required to provide claim charts for each member of each accused chip family, this would result in over 12,000 claim charts. Rather than penalize TPL for trying to streamline the case, TPL should be commended.
None of the defendants have demonstrated the existence of material prejudice; and all of the legal factors for correction of the PICs weigh in TPL's favor.
The motion should be granted. Case 2:05-cv-00494-TJW Document 122 Filed 09/07/2006 Page 5 of 21
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II. TPL HAS ESTABLISHED THAT GOOD CAUSE EXISTS TO PERMIT IT TO CORRECT ITS PRELIMINARY INFRINGEMENT CONTENTIONS
A. Defendants Do Not Oppose TPL's Motion As It Relates To Conforming The Text Of The PICs To The Claim Charts.
As an initial matter, Defendants do not oppose TPL's motion to correct the text of the PICs to conform the list of p roduct numbers and claims asserted in the claim charts, except that Toshiba (but not NEC and MEI) opposes any correction to the PICs as it relates to the '148 patent because Toshiba believes the claim charts do not support a claim for infringement. While TPL will show that Toshiba is wrong, as the memory need not be limited to the DRAM, the issue of the sufficiency of TPL's proof of infringement is not before this Court. Further, Patent Local Rule 3-1 "does not require [plaintiff] to produce evidence of infringement
or to set forth ironclad and irrefutable claim constructions, nor does it require a plaintiff to provide support for its contentions." Renasas Tech Corp. v. Nanya Tech. Corp., 2004 WL 26000466, *3-4 (N.D.Cal. Nov. 10, 2004) (quoting Network Caching Technology Corp. v.
Novell, Inc., 2003 WL 21699799 *4 (N.D.Cal. March 21, 2003)).1 Consequently, TPL's motion to correct the text of the PICs to conform to the list of product numbers and the identity of claims asserted in the claim charts should be granted. B. It Was Not Per Se Inappropriate Under Patent Local Rule 3-1 For TPL To Have Provided Claim Charts For Representative Chips Of A Chip Family, Rather Than For All Chips In A Family. Toshiba and NEC vigorously assert (without case authority) that it is per se improper for
TPL to provide claim charts for representative chips of a chip family, rather than forall chips in 1 This Court has found that although the Northern District of California's opinion is not binding on this Court, it is persuasive because the relevant portions of the Court's Patent Rule 3-1 are exactly the same as Northern District of California Patent LR 3-1. STMicroelectronics, Inc. v. Motorola, Inc., 308 F.Supp.2d 754 (E.D.Tex. 2004). Case 2:05-cv-00494-TJW Document 122 Filed 09/07/2006 Page 6 of 21 - 3 - the family.
MEI, however, concedes that there is nothing per se improper with this approach, and has provided supporting case authority: "Of course it would be acceptable to provide a single chart for a series of products when there is a fair basis to believe that the separate products are the same for purposes of infringement," MEI Opp., page 5, citing Renasas, 2004 WL 26000466, Not Reported in F.Supp.2d (N.D.Cal. Nov. 10, 2004). In Renesas, the defendant moved to strike the plaintiff's PICs because they included a single claim chart for 160 accused products. The court denied the motion because the Northern District of California's Patent Local Rule 3-1, which is identical to this Court's Patent Local Rule 3-1 "only requires 'a chart identifying specifically where each element of each asserted claim is found within each Accused Instrumentality,' and not a separate chart for each individual product." Id. at *2 (emphasis added.)
Just like the California rule, this Court's Patent Local Rule 3-1 merely requires TPL to provide Defendants a "chart identifying specifically where each element of each asserted claim is found within each Accused instrumentality," rather than a claim chart for each of the hundreds of individual chips and end-user products embodying those products that are at issue in this lawsuit.
In compliance with this rule, TPL has provided Defendants with more than 600 claim charts. Defendants correctly note that this Court's Patent Local Rules are designed to streamline the discovery process and enable the parties to move efficiently toward claim construction and the eventual resolution of their dispute. However, Toshiba and NEC (but not MEI) seemingly ignore that the Patent Local Rules are also intended “to strike a balance of providing fair notice
to defendants without requiring unrealistic, overly factual contentions from plaintiffs,” as the “burden of notice the Patent Rules place on plaintiffs is intended to be a shield for defendants not Case 2:05-cv-00494-TJW Document 122 Filed 09/07/2006 Page 7 of 21 - 3 - the family.
MEI, however, concedes that there is nothing per se improper with this approach, and has
provided supporting case authority: "Of course it would be acceptable to provide a single chart
for a series of products when there is a fair basis to believe that the separate products are the
same for purposes of infringement," MEI Opp., page 5, citing Renasas, 2004 WL 26000466,
Not Reported in F.Supp.2d (N.D.Cal. Nov. 10, 2004). In Renesas, the defendant moved to strike
the plaintiff's PICs because they included a single claim chart for 160 accused products. The
court denied the motion because the Northern District of California's Patent Local Rule 3-1,
which is identical to this Court's Patent Local Rule 3-1 "only requires 'a chart identifying
specifically where each element of each asserted claim is found within each Accused Instrumentality,' and not a separate chart for each individual product." Id. at *2 (emphasis added.)
Just like the California rule, this Court's Patent Local Rule 3-1 merely requires TPL to provide Defendants a "chart identifying specifically where each element of each asserted claim is found within each Accused Instrumentality," rather than a claim chart for each of the hundreds of individual chips and end-user products embodying those products that are at issue in this lawsuit.
In compliance with this rule, TPL has provided Defendants with more than 600 claim charts. Defendants correctly note that this Court's Patent Local Rules are designed to streamline the discovery process and enable the parties to move efficiently toward claim construction and the eventual resolution of their dispute. However, Toshiba and NEC (but not MEI) seemingly ignore that the Patent Local Rules are also intended “to strike a balance of providing fair notice
to defendants without requiring unrealistic, overly factual contentions from plaintiffs,” as the “burden of notice the Patent Rules place on plaintiffs is intended to be a shield for defendants not Case 2:05-cv-00494-TJW Document 122 Filed 09/07/2006 Page 7 of 21 - 3 - n compliance with this rule, TPL has provided Defendants with more than 600 claim charts. Defendants correctly note that this Court's Patent Local Rules are designed to streamline the discovery process and enable the parties to move efficiently toward claim construction and the eventual resolution of their dispute. However, Toshiba and NEC (but not MEI) seemingly
ignore that the Patent Local Rules are also intended “to strike a balance of providing fair notice to defendants without requiring unrealistic, overly factual contentions from plaintiffs,” as the “burden of notice the Patent Rules place on plaintiffs is intended to be a shield for defendants.
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a sword.” Orion IP, LLC v. Staples, Inc., 407 F.Supp.2d 815, 817-818 (E.D.Tex. 2006). TPL, by providing Defendants a chip that is representative of each family of chips
accused of infringement, has satisfied both the letter and the spirit of the Patent Local Rules by giving Defendants fair notice of the nature and scope of its infringement contentions. To require TPL to provide claim charts for the hundreds of additional chips that are within the families
accused of infringement would be unduly burdensome and, more importantly, is not likely to provide Defendants with information beyond that which has already been provided.
Defendants also claim that they were not previously on notice that TPL was accusing entire chip families (and not just individual chips) of infringement. This contention is easily belied by the letters from TPL to Defendants attached as Exhibits 2 and 3 to TPL's motion. These letters and their attachments, dated June 27 and 28, 2006, both refer to "representative" chips and the June 28 letter identifies the “family” to which they belong. Why would TPL
specifically identify the “family” to which each accused chip belongs if it was not accusing the entire family of infringement? Defendants have offered no other interpretation. It is improper for Defendants to rely on discrepancies between the June 27 and 28, 2006 letters and the corrected PICs to disadvantage TPL. TPL provided the list of accused chips on the condition that the lists were provided simply as "an accommodation and convenience to
assist [defendants] in preparing for discovery, [several weeks] in advance of the deadline for TPL to provide its infringement contentions, without prejudice to subsequent modification: These lists are [sic] being provided to you in confidence, subject to the proposed and anticipated protective order, as an accommodation and convenience to assist you in preparing for discovery, in advance of the deadline for TPL to provide its infringement contentions, without prejudice to subsequent modification, such as by adding additional products, or by deleting products. You may share these lists with client representatives, as
reasonably necessary, so long as they understand and agree that they will be bound by the protective order.
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These lists are also provided to you with the further understanding that they may not be used in this litigation as evidence that any particular products are or are not covered by the patents, or any of them. Any persons who finds these conditions unacceptable should promptly double delete his or her lists, and not retain or share copies until we can reach a mutually agreeable understanding.
(TPL's Motion, Exh. 2 (emphasis added.)). This accommodation was not part of a bargain of any sort. It was simply a unilateral, voluntary, good-faith gesture by TPL in response to a request by the Defendants for an advance
look at the infringement contentions, and it was made expressly without prejudice. As a result, the Defendants' reliance upon these letters as evidence of alleged admissions by TPL (MEI Opp., p. 2, 3), or to attack TPL's good faith (Toshiba Opp., 3-7), or to assert that the "defendants were frustrated by a plaintiff that seems to change its infringement theory every week" (Toshiba Opp.,
p. 6), or otherwise disadvantage TPL, are contrary to the letter and spirit of the conditions under which they were provided, and should not be taken into account by the Court in deciding the present motion. To accuse TPL of having a “cavalier and lackadaisical approach” to compliance with this Court's rules (as Toshiba does) because the lists of products identified in the PICs may differ in minor respects to earlier lists (as TPL stated they may) is inappropriate and will likely serve only to hinder future cooperation among the parties.2 2 The fact that TPL further revised and refined the corrected PICs between the date on which TPL sent Defendants the proposed corrected PICs and requested a meet and confer conference, and the date on which TPL filed its motion, does not meant that TPL failed to meet and confer in accordance with this Court's rules. It shows only that TPL was diligent in attempting to ensure
that the corrected PICs were free from error.
Case 2:05-cv-00494-TJW Document 122 Filed 09/07/2006 Page 9 of 21 p. 6), or otherwise disadvantage TPL, are contrary to the letter and spirit of the conditions under which they were provided, and should not be taken into account by the Court in deciding the present motion. To accuse TPL of having a “cavalier and lackadaisical approach” to compliance with this Court's rules (as Toshiba does) because the lists of products identified in the PICs may differ in minor respects to earlier lists (as TPL stated they may) is inappropriate and will likely serve only
to hinder future cooperation among the parties. 2 The fact that TPL further revised and refined the corrected PICs between the date on which TPL sent Defendants the proposed corrected PICs and requested a meet and confer conference,
and the date on which TPL filed its motion, does not meant that TPL failed to meet and confer in accordance with this Court's rules. It shows only that TPL was diligent in attempting to ensure that the corrected PICs were free from error.
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C. The Chips For Which TPL Provided Claim Charts Are, For Purposes Of Infringement, Representative Of The Families To Which They Belong. Defendants argue that TPL's motion to correct its PICs should be denied because the rrepresentative chips are purportedly not representative of the families accused of infringement. This argument is a red herring. TPL is not claiming that there are no differences between the representative chips for which claim charts have been provided and the other chips in the
associated family. Obviously, there are some differences as the chips have different part numbers and may have different packaging and/or different application-specific uses. However, TPL has alleged (and Defendants have not persuasively refuted) these differences are not
material to a determination of whether the accused chips infringe the patents-in-suit. To the extent Defendants contend the differences in the few examples they have come up with impact the infringement analysis, the issue should be addressed via a summary judgment or other dispositive motion, but not here. The only issue raised by TPL's motion is whether TPL has shown good cause to correct its PICs. It has. Notwithstanding, as shown below, Defendants'
claims that the representative chips are not representative for purposes of infringement are, simply put, incorrect.
1. Toshiba TX-49 Family ('336 patent): Toshiba contends the TX4937 product is not representative of the entire TX-49 family because the TX4937 product for which a claim chart
has been provided uses one phase-locked loop (PLL) while another product in the family, the TX4939 processor, uses two PLLs that operate at different frequencies. Toshiba claims that “these differences are at the heart of the structure relevant to the '336 patent claims,” but omits an
explanation of why this is supposedly so. Instead, Toshiba demands claim charts that explain how the "an entire ring oscillator system clock" limitation of the claims of the '336 patent reads on two PLLs. However, Case 2:05-cv-00494-TJW Document 122 Filed 09/07/2006 Page 10 of 21
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additional claim charts are not required for those chips that have two PLLs as the infringement analysis is the same as it is for those chips that have one PLL. As Toshiba is well aware, it is an established principle of patent law that the inclusion of additional structure does negate
infringement. Canon Computer Sys. v. Nu-Kote Int'l, 134 F.3d 1085, 1090 (Fed. Cir. 1998). Moreover, the question of how "an entire ring oscillator system clock" limitation reads on two PLLs does not affect the sufficiency of TPL's corrected PICs and the accompanying claim charts. At most, it may be a claim construction issue. TC280 Family ('584 patent): Toshiba contends the claim charts are deficient because the TC280 family of ASICs can be used with different microprocessors cores, such as ARMbased cores and MIPS-based cores, and since TPL provided a claim chart for only the ARMbased cores, TPL's claim charts are deficient. Toshiba's argument fails because TPL is accusing only those chips with ARM-based cores of infringement of the '584 patent, as evidenced by the fact that every representative Toshiba ASIC chip accused of infringing the '584 patent in the PICs is noted as having an ARM core. Also, because these ASIC chips are designed by the customer for application-specific uses, right down to the circuitry used on the chip, there is no existing line of pre-designed chips to identify . Thus, there is no need to provide claim charts for non-ARM-based cores.3 TLCS-870/X Family ('148 patent): Because the numerous chips within a family of
chips may differ in ways that are material to a determination of whether the chips infringe the 3 This issue, like Defendants' other claims that the epresentative chips are not representative of the families to which they belong, easily could have been resolved during the parties' meet and confer. However, under no circumstance were Defendants willing to allow TPL to correct its PICs to specifically identify the families of chips because they want to limit their exposure and the potential damages to just individual chips. Case 2:05-cv-00494-TJW Document 122 Filed 09/07/2006 Page 11 of 21
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'148 patent, TPL has not accused entire families of infringing the '148 patent. Rather, it has accused specific chips and provided claim charts for such chips. See, e.g. TPL's corrected PICs at pp. 12-14. Thus, Toshiba's arguments about the sufficiency of TPL's claim charts for the '148 patent also fail.
2. NEC NEC focuses on the limitations of the claims of the '336 patent that the system include "an on-chip input/ouput interface connected to exchange coupling control signals, addresses and data"; and a "second clock . . . connected to said input/output interface." NEC attempts to highlight structural differences among chips as proof that TPL's PICs are deficient, based on these limitations. Under TPL's contentions, however, all of the chips of the chip families are the same for infringement purposes. Therefore, what NEC is really arguing is that under its claim construction, it believes that some chips do not infringe. As discussed, NEC's arguments should
not go to the sufficiency of TPL's PICs, but rather should be part of future motions challenging infringement as the case is further developed. 8-Bit 179K Series (78KOS core) ('336 patent): NEC notes that in the user manual for
this chip family, which includes the representative chip (uPD78F9328) as well as other chips, only the uPD78F9328 chip contains a serial interface. NEC argues that this shows that the representative chip is not identical to the other chips in this family. However, again, while there
are undeniably differences between chips in a family, only differences that impact whether a chip infringes the patents-in-suit are relevant. Thus, because this same user manual explains that the ports of the other chips in this family can be used to move data into and out of the chip in
response to certain events, which TPL believes also meets the "input/output interface" and "second clock" limitations of the claims of the '336 patent, these differences do not affect the infringement commonality of the chips in the chip family.
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Digital Signal Processor Devices ('336 patent): NEC inappropriately relies on an oversight by TPL (TPL inadvertently erred by using a schematic of the uPD77115 chip from a user manual that also describes the uPD77111 chip when analyzing the UPD77111 chip) to argue that all of TPL's claim charts are deficient because the chips are not representative of their families. This oversight does not mean TPL's claim charts do not satisfy Patent Local Rule 3-1.
They do. Instead, this is an error that, if deemed necessary by this Court, can easily be cured by having TPL provide a corrected claim chart. Furthermore, TPL submits that either the UPD77115 or the uPD77111 chips can be the
representative chip for the "Digital Signal Processor Devices" family of chips to which they both belong. As NEC undoubtedly knows from a review of TPL's other claim charts, TPL asserts that the "on-chip input/output interface" limitation of the '336 patent is met by various types of interfaces, not just the "audio serial interface" found in the uPD77115 chip. The uPD77111 chip has at least two other interfaces, a "serial interface
#1" and a "serial interface
#2," which TPL believes also satisfy the "on-chip input/output interface" limitation. This difference is just one example of the manner in which a representative chip for which claim charts have been provided differs from other chips within the family in ways that are not material to the question of infringement. 4-Bit 17k Series ('336 patent): The difference in the number of pins in the serial
interface of the uPD17717 chip and the number of pins in the serial interface of the other chips in the "4-Bit 17K Series" chips is another example of the manner in which a representative chip may differ from other chips in the same family in ways that are not relevant to the question of
infringement. The pertinent claim limitations do not specify the number of pins required for the "inpout/output interface," and in fact make no mention of specific pins. While some of the Case
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claims do require that the interface be connected to exchange "control signals, addresses, and data," and that a "second clock" be connected to the interface, these limitations can be (and indeed are) met by a variety of pinout configurations. Thus, if a serial interface has a clock pin, a single data input pin and a single data output pin --TPL believes all chips in the 4-Bit 17k Series
family have at least these 3 pins -- the "on-chip input/output interface" and "second clock" limitations of the '336 patent are satisfied. Additional pins, if any, do not negate infringement nor change the infringement analysis. See Canon Computer Sys., 134 F.3d at 1090.
3. MEI As an initial matter, MEI attempts to muddy the water by arguing that the chips for which TPL provided claim charts cannot be representative of other chips in the family because TPL provided claim charts for different chips in the same family, and alleged that the different chips infringe different patents. But TPL provided MEI claim charts for different representative chips
for the different patents-in-suit to provide Defendants the widest range of information concerning infringement.4 It is the chip families that are the sets of chips being accused of infringement; the representative chips are merely one example of a chip within the chip family. In some cases,
TPL provided a claim chart for more than one representative chip for each chip family. In other cases, TPL used one representative chip from a chip family for its infringement analysis under one patent, and a different representative chip from the same chip family for its infringement analysis under a different patent. The particular representative chip selected is not meant to exclude or otherwise determine subsets of the associated chip family for infringement purposes. MN101 Family ('336 patent): MEI asserts that the claim charts for the MN101 family 4 As discussed above, for the '148 patent, TPL is accusing individual chips, not families of chips, of infringement.
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are deficient because the claim chart for the MN101CF91D chip identifies the "I2C bus" connected through the "SCL2 pin" as meeting the "second clock" limitation, but this bus is not present in all products in the MN101 family, specifically the MN101C115 chip. However, the MN101C115 chip has a serial interface with a clock input, which does meet the "second clock" limitation. Therefore, while the configuration between these chips is somewhat different, the
difference is not material to the infringement analysis.
MN103 Family ('336 patent): MEI asserts that the claim charts for the MN103 family are deficient because TPL provided claim charts for two representative chips, the MN103E010H and MN103SC2A, and alleged that different components satisfy the "second clock" limitation
for each chip. Again, these differences are not material to the infringement determination because both chips have a serial interface with a clock pin, a data input pin and a data output pin. Indeed, these charts illustrate TPL's contention that a number of different I/O interfaces meet the relevant limitations of the '336 patent claims.
MN103 Family (584 patent): MEI argues that because TPL's claim charts for two representative chips for the MN103 family show that the chips have different instruction formats (one has 11 instruction formats and the other has 16 instruction formats), neither chip is representative of the family. This is false. As shown in the claim charts, the "instruction groups" limitation of claim 29 of the '584 patent, which requires predetermined locations of at least some operand or instruction references relative to the instruction groups, is satisfied for at least the branch instruction, which appears to be common to both representative chips. The number of instruction formats is not relevant to the infringement analysis. MN101 Family ('148 patent): As discussed above, TPL is accusing individual chips, not families, of infringing the '148 patent.
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are deficient because the claim chart for the MN101CF91D chip identifies the "I2C bus" connected through the "SCL2 pin" as meeting the "second clock" limitation, but this bus is not present in all products in the MN101 family, specifically the MN101C115 chip. However, the MN101C115 chip has a serial interface with a clock input, which does meet the "second clock" limitation. Therefore, while the configuration between these chips is somewhat different, the
difference is not material to the infringement analysis.
MN103 Family ('336 patent): MEI asserts that the claim charts for the MN103 family are deficient because TPL provided claim charts for two representative chips, the MN103E010H and MN103SC2A, and alleged that different components satisfy the "second clock" limitation for each chip. Again, these differences are not material to the infringement determination because both chips have a serial interface with a clock pin, a data input pin and a data output pin. Indeed, these charts illustrate TPL's contention that a number of different I/O interfaces meet the relevant limitations of the '336 patent claims.
MN103 Family (584 patent): MEI argues that because TPL's claim charts for two representative chips for the MN103 family show that the chips have different instruction formats (one has 11 instruction formats and the other has 16 instruction formats), neither chip is representative of the family. This is false. As shown in the claim charts, the "instruction groups" limitation of claim 29 of the '584 patent, which requires predetermined locations of at least some operand or instruction references relative to the instruction groups, is satisfied for at least the
branch instruction, which appears to be common to both representative chips. The number of instruction formats is not relevant to the infringement analysis. MN101 Family ('148 patent): As discussed above, TPL is accusing individual chips, not families, of infringing the '148 patent.
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D. TPL's Identification Of Chips Within A Family Is Based On Publicly Available Information. Toshiba and NEC (but not MEI) contend the website pages attached as the "clarifying"
exhibits to TPL's corrected PIC, which provide web pages that identify the chips that make up each accused family of chips, are "junk." Even a cursory review of the clarifying exhibits proves both Toshiba and NEC wrong. At best, Toshiba's and NEC's complaints are premature. Indeed,
TPL painstakingly bookmarked each PDF with the names of the representative chips, linking each representative chip to the corresponding web pages (or groups of web pages) in the exhibit. However, because of the constraints on the size of documents that can be filed electronically with the Court, TPL had to break down its originally bookmarked master exhibits into numerous smaller exhibits without bookmarks. Thus, TPL has not yet served the bookmarked exhibits on
Defendants, but will do so if the Court grants permission for TPL to correct its PICs. These bookmarks will provide even further information to Defendants on which web pages correspond to which chip families, even though each defendant is already in the best position to understand
its own product classifications, which TPL used to delineate the chip families. NEC claims that TPL uses family designations that are not used by NEC. To the extent
TPL uses the incorrect nomenclature when referring to NEC's family of products, the names were obtained from NEC's website. NEC, not TPL, is in the best position to provide more accurate information, if TPL has used incorrect nomenclature. E. Defendants Have Failed To Refute TPL's Showing That Good Cause Exists To Correct Its PICs.
TPL established the consideration of the four factors to be considered in deciding its motion to correct its PICs --(1) the explanation for the failure to meet the deadline, (2) the importance of the thing that would be excluded, (3) potential prejudice in allowing the thing that would be excluded, and (4) the availability of a continuance to cure such prejudice-- weighs
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D. TPL's Identification Of Chips Within A Family Is Based On Publicly Available Information. Toshiba and NEC (but not MEI) contend the website pages attached as the "clarifying"
exhibits to TPL's corrected PIC, which provide web pages that identify the chips that make up each accused family of chips, are "junk." Even a cursory review of the clarifying exhibits proves both Toshiba and NEC wrong. At best, Toshiba's and NEC's complaints are premature. Indeed,
TPL painstakingly bookmarked each PDF with the names of the representative chips, linking each representative chip to the corresponding web pages (or groups of web pages) in the exhibit. However, because of the constraints on the size of documents that can be filed electronically with the Court, TPL had to break down its originally bookmarked master exhibits into numerous smaller exhibits without bookmarks. Thus, TPL has not yet served the bookmarked exhibits on
Defendants, but will do so if the Court grants permission for TPL to correct its PICs. These bookmarks will provide even further information to Defendants on which web pages correspond to which chip families, even though each defendant is already in the best position to understand
its own product classifications, which TPL used to delineate the chip families. NEC claims that TPL uses family designations that are not used by NEC. To the extent
TPL uses the incorrect nomenclature when referring to NEC's family of products, the names were obtained from NEC's website. NEC, not TPL, is in the best position to provide more accurate information, if TPL has used incorrect nomenclature. E. Defendants Have Failed To Refute TPL's Showing That Good Cause Exists To Correct Its PICs.
TPL established the consideration of the four factors to be considered in deciding its motion to correct its PICs --(1) the explanation for the failure to meet the deadline, (2) the importance of the thing that would be excluded, (3) potential prejudice in allowing the thing that would be excluded, and (4) the availability of a continuance to cure such prejudice-- weighs
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apiece and, as result, for the '584 patent, has provided Defendants with 26 claim charts. However, there are on the order of ____ family members (80 for Toshiba, 89 for MEI, 79 for NEC and ___ for Fujitsu). If NEC's request were granted, this would result in on the order of 400 claim charts for the '584 patent. NEC's request should be denied.
2. MEI's Proposed Alternate Remedy Would Unfairly Penalize TPL and Could Provide Defendants With an Undeserved Windfall. MEI requests that, if TPL is permitted to employ claim charts for representative chips, rather than claim charts for all members of all accused families of chips, TPL should be permitted discovery as to only the representative chips, but the Defendants should be left free to prove that certain chips do not infringe for reasons independent of the reasons why the representative chips do not infringe; and that, if Defendants are able to prove that any particular chip in a family does not infringe, that showing would apply to all chips within the chip families. MEI Opp., page 9. This request should be denied because it would unfairly penalize TPL, and could provide Defendants with an undeserved windfall. If by chance a Defendant believes that one or more family members do not infringe a patent-in-suit for reasons materially different from its defense to infringement by the representative chip, the Defendant would be able to make its proofs. MEI is asking for a ruling which would permit a single non-infringing family member to exonerate hundreds of infringing family members. This case should be decided on its merits, not on the basis of an undeserved penalty to TPL. The object of PICs is to provide Defendants notice of TPL's infringement allegations. Patent Local Rule 3-1 "does not require [plaintiff] to produce evidence of infringement or to set forth ironclad and irrefutable claim constructions, nor does it require a plaintiff to provide
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support for its contentions." Renasas, 2004 WL 26000466, at *3-4 (quoting Network Caching Technology Corp. v. Novell, Inc., 2003 WL 21699799 *4 (N.D.Cal. March 21, 2003).
TPL has already provided Defendants with more than 600 claim charts. TPL has more than adequately met its notice obligations under the patent local rules. Given the scope of the Defendants' infringement -- a problem caused by Defendants, not TPL -- TPL has been "as specific as possible" as required by Patent Local Rule 3-1 (b), contrary to Toshiba's assertions. See Toshiba Opp., p. 10.
3. TPL's Proposal to Limit Discovery. To the extent that MEI's foregoing proposal suggests that discovery be limited to the representative chips, TPL has already proposed this to the Defendants, with the additional proviso that, for any given family, discovery as to family members other than the representative chip be limited to discovery as to any reasons why the Defendants they do not infringe for
reasons other than asserted on behalf of the representative chips. TPL believes this would be workable, and would go a long way towards streamlining this case for discovery and trial.
III. CONCLUSION
TPL respectfully requests that this Court grant its motion to correct its PICs to (1) conform the list of products in the text of the PIC to the products for which claim charts were provided; (2) clarify that the chip families, not just individual chips that are representative of the chip families, are accused of infringement; and (3) conform the list of asserted claims of the patents-in-suit in the text of the PIC to the claim charts. DATED: September 7, 2006
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